Radio apparatus and radio receiving method

ABSTRACT

A radio apparatus includes a receiver which receives a wirelessly transmitted signal as a reception signal, a transmitter which is provided in the vicinity of the receiver and generates a transmission signal having a frequency different from that of the reception signal, and a reception signal extracting unit which extracts a reception signal from an input signal containing the reception signal and the transmission signal, at a timing of a zero crossing of the transmission signal in the input signal, by using phase information including the phase of the transmission signal from the transmitter.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application 2007-258008 filed on Oct. 1, 2007;the entire contents of which are incorporated herein by this reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a radio apparatus and radio receivingmethod capable of performing radio transmission and reception at thesame time.

2. Description of the Related Art

Multimode radio apparatuses have been made available in recent yearsthat are radios or radio devices that can be used in multiple modes suchas multiple frequency bands.

For example, Japanese Patent Application Laid-Open Publication No.2000-13274 discloses a multimode radio apparatus including CDMA (CodeDivision Multiplex Access) and PDC (Personal Digital Cellular System)transmission units. The technique in Japanese Patent ApplicationLaid-Open Publication No. 2000-13274 can reduce the number of componentsin transmission units by sharing circuits between the wideband CDMA andPDC transmission units.

Japanese Patent Application Laid-Open Publication No. 2003-133981discloses a reception unit of a multimode radio apparatus that receiveswideband and narrowband signals. The technique in Japanese PatentApplication Laid-Open Publication No. 2003-133981 can reduce the size ofthe apparatus by sharing circuits of the reception unit between the twomodes.

When transmission and reception of signals are performed based on morethan one standard in an apparatus, that is, transmission is performedbased on one standard and reception is performed based on anotherstandard, a signal transmitted by the apparatus cross-talks into asignal received by the apparatus.

In that case, the reception signal intensity becomes very strong becausethe transmitting and receiving circuits are close to each other.Consequently, the transmission signal acts as an interference wave ornoise that interferes with the target reception signal that the receiveris expected to receive.

Japanese Patent Application Laid-Open Publication No. 2007-505591discloses that a vector multiplier is used in a multimode radiotransmission and reception unit to reduce or eliminate interference witha receiver caused by a transmitter while the transmitter is transmittinga transmission signal to an antenna and at the same time a receiver isreceiving a signal in another mode from the antenna.

The vector multiplier controls the phase and amplitude of noise thatcross-talks into the receiver (that is, spurious noise).

The configuration for adjusting the phase and amplitude as described inJapanese Patent Application Laid-Open Publication No. 2007-505591 hasthe drawback that the configuration increases the complexity and size ofthe circuitry as well as the cost.

SUMMARY OF THE INVENTION

A radio apparatus according to one aspect of the present inventionincludes: a receiver configured to receive as a reception signal awirelessly transmitted signal; a transmitter provided in the vicinity ofthe receiver and configured to generate a transmission signal to bewirelessly transmitted with a frequency different from that of thereception signal; and a reception signal extracting unit provided in thereceiver and configured to extract a reception signal from an inputsignal containing the reception signal and the transmission signal, at atiming of a zero crossing of the transmission signal in the inputsignal, by using phase information including a phase of the transmissionsignal from the transmitter.

A radio apparatus according to another aspect of the present inventionincludes: a receiver configured to receive as a reception signal awirelessly transmitted signal; a transmitter provided in the vicinity ofthe receiver and configured to generate a transmission signal to bewirelessly transmitted with a frequency different from that of thereception signal; a transmission signal generating unit provided in thetransmitter and configured to generate phase information of thetransmission signal; and a reception signal extracting unit provided inthe receiver and configured to extract a reception signal from an inputsignal containing the reception signal and the transmission signal, at atiming of a zero crossing of the transmission signal in the inputsignal, by using the phase information input from the transmissionsignal generating unit.

A radio receiving method according to one aspect of the presentinvention using a receiver configured to receive as a reception signal awirelessly transmitted signal and a transmitter provided in the vicinityof the receiver and configured to generate a transmission signal to bewirelessly transmitted with a frequency different from that of thereception signal detects a timing of a zero crossing of the transmissionsignal in the input signal, from the input signal in the receivercontaining the reception signal and the transmission signal, by usingphase information including a phase of the transmission signal from thetransmitter and extracts the reception signal at the detected timing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a radio system including a multimode radioapparatus according to a first embodiment of the present invention;

FIG. 2 is a block diagram showing a configuration of a reception signalextracting unit provided in a receiver constituting the multimode radioapparatus;

FIG. 3 is a diagram illustrating a configuration and operation of asampling circuit constituting the reception signal extracting unit;

FIGS. 4A to 4F are diagrams illustrating operations of components of thereception signal extracting unit before delay adjustment;

FIGS. 5A to 5F are diagrams illustrating operations of the components ofthe reception signal extracting unit after the delay adjustment;

FIG. 6 is a diagram showing an example of the result of a simulation ofthe operations shown in FIGS. 5A to 5F;

FIG. 7 is a block diagram showing a configuration of a reception signalextracting unit according to a variation of the first embodiment;

FIGS. 8A and 8B are diagrams illustrating a periodic control operationfor adjusting a delay amount according to the variation;

FIG. 9 is a block diagram showing a configuration of a receiveraccording to a second embodiment of the present invention; and

FIG. 10 is a circuit diagram showing an exemplary configuration of adelay adjusting circuit according to a variation of the secondembodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described with reference tothe accompanying drawings.

First Embodiment

FIG. 1 shows a radio system 2 including a multimode radio apparatus 1according to a first embodiment of the present invention.

The radio system 2 includes the multimode radio apparatus 1 according tothe first embodiment and a transceiver or a transmission base station(hereinafter referred to as a transceiver) 3 which communicates with themultimode radio apparatus 1.

The multimode radio apparatus 1 includes one or more transmitters andone or more receivers. In the exemplary configuration shown in FIG. 1and described below, one transmitter 4 and one receiver 5 are included.In the present embodiment, the multimode radio apparatus 1 has thecapability of performing transmission and reception at the same time aswill be described below. While the first embodiment will be describedwith respect to the multimode radio apparatus 1, the present inventioncan be widely applied to radio apparatuses having the capability ofperforming transmission and reception at the same time.

The transmitter 4 transmits a transmission signal TX1 generated at thetransmitter 4 to the outside (of the multimode radio apparatus 1)through an antenna 6 a. The transceiver 3 receives the transmissionsignal TX1 through an antenna 7. The transceiver 3 transmits atransmission signal TX to the outside of the transceiver 3 through theantenna 7.

The receiver 5 receives the transmission signal TX transmitted from thetransceiver 3, for example, as a reception signal RX through an antenna6 b. While separate antennas 6 a and 6 b are used for transmission andreception in the multimode radio apparatus 1 in FIG. 1, a common antennamay be used instead.

While the receiver 5 is intended to receive the reception signal RX, thereceiver 5 also receives the transmission signal TX1 transmitted fromthe transmitter 4 in addition to the target reception signal RX becausethe transmitter 4 is located in the vicinity of the receiver 5.

The transmitter 4 in the multimode radio apparatus 1 according to thefirst embodiment provides a transmission signal TX2 (specifically, aclock signal, which will be described below) having phase information ofthe transmission signal TX1 to the receiver 5. The receiver 5 includes areception signal extracting unit 11 configured to use the phaseinformation of the transmission signal TX2 to cause a delay adjustingcircuit 10 to adjust a delay amount to cancel or reduce the transmissionsignal TX1 in an input signal in extracting a reception signal.

FIG. 2 shows a configuration of the reception signal extracting unit 11provided in the receiver 5.

The target reception signal RX to be received and the transmissionsignal TX1 are input in the receiver 5 as input signals (through theantenna 6 b). The input signals are amplified by an amplifier 12 andthen input in the reception signal extracting unit 11. Symbols (fR) and(fT) suffixed to the reception and transmission signal symbols RX andTX1 in FIG. 2 denote the frequencies of the signals. The same symbolsare also used in FIGS. 4A to 4F and 5A to 5F described later.

The reception signal extracting unit 11 includes a sampling circuit 13configured to sample the reception signal RX and transmission signalTX1, which are input signals, a first low-pass filter (abbreviated asfirst LPF) 14 configured to extract a reception signal component in apredetermined frequency band from the output signal of the samplingcircuits 13, a buffer amplifier 15, and a delay adjusting circuit 10including a second LPF 14 b configured to extract DC component from anoutput signal of the sampling circuit 13, and other components. Thebuffer amplifier 15 in FIG. 2 may be omitted from the configuration.

The delay adjusting circuit 10 includes the second LPF 14 b configuredto extract a DC component, an analog control circuit 16 configured touse an output signal of the second LPF 14 b to adjust (or control) thetiming of sampling in the sampling circuit 13, and a delay circuit 17configured to vary the phase amount (more specifically, the amount ofdelay) of a clock signal for sampling under the control of the controlcircuit 16.

The control circuit 16 performs control to adjust the amount of delay onthe basis of the output signal of the second LPF 14 b so that the timingof sampling of an input signal in the sampling circuit 13 issynchronized with a zero crossing timing at which the transmissionsignal TX1 crosses a zero level (zero potential).

The control circuit 16 includes an operational amplifier (hereinafterabbreviated as op-amp) 16 a configured to output a difference signal,for example.

The op-amp 16 a adjusts the amount of delay of the delay circuit 17 by adifference signal resulting from comparing a second LPF output signalapplied to an inverting input terminal with the zero potential(reference potential) at a noninverting input terminal grounded.

The delay circuit 17 is configured with a variable delay element, forexample, whose delay amount can be varied (adjusted). A transmissionsignal TX2 having phase information of the transmission signal TX1 ofthe transmitter 4 is input in the delay circuit 17, which delays thetransmission signal TX2.

The transmission signal TX2 consists of a clock signal φo1 generatedfrom the transmission signal TX1 and a clock signal φo2 of oppositephase to the clock signal φo1.

The clock signals φo1 and φo2 pass through the delay circuit 17 andbecome clock signals φ1, φ2 acting as a sampling signal. The samplingcircuit 13 samples an input signal by the clock signals φ1, φ2.

The op-amp 16 a performs control to automatically adjust the amount ofdelay, that is, the phase of the sampling signal, so that the value ofthe difference signal, in particular, the output signal of the secondLPF 14 b becomes zero (or the difference between the output signal andthe zero reference potential is minimized).

For example, a control loop is formed that adjusts the amount of delay(phase amount) according to the phase relation between the timing(phase) of a zero crossing of the transmission signal TX1 and the timing(phase in which the input signal is sampled) of a trailing edge of theclock signal φ1 so that the difference between the phases decreases, asshown in FIGS. 4A to 4F, which will be described below.

In the case shown in FIGS. 4A to 4F, the difference signal from theop-amp 16 a is used to adjust the length of delay of the delay circuit17 so that the phase of the clock signal φ1 shifts to the right, inother words, the phase delays. Although not shown in FIGS. 4A to 4F, ifa trailing edge of the clock signal φ1 is delayed from the phase of azero crossing of the transmission signal TX1, the polarity of thedifference signal is reversed. In that case, the amount of delay isadjusted to shift the trailing edge of the clock signal φ1 to the left,that is, to advance the phase.

In this way, the delay adjusting circuit 10 in the present embodimentincludes the control loop that automatically adjusts the phase of thesampling signal for sampling an input signal so that the phase becomes apredetermined phase on the basis of the output signal of the samplingcircuit 13.

The control loop controls the amount of delay so that a trailing edge ofthe clock signal φ1, that is, the timing of sampling, is set at thetiming of a zero crossing of the transmission signal TX1 as shown inFIGS. 5A to 5F and the setting state is maintained.

The first LPF 14 a is set to have an LPF characteristic that passes asignal of a frequency component of |fR−fT|, where fR is the frequency ofthe reception signal RX and fT is the frequency of the transmissionsignal TX1. The second LPF 14 b is set to have an LPF characteristicthat passes a DC component as stated above.

An output signal of the first LPF 14 a is input in a demodulation block18 through the buffer amplifier 15. The demodulation block 18demodulates the reception signal RX.

Operation in FIG. 2 will be outlined below. A reception signal RX and atransmission signal TX1 are input in the sampling circuit 13 and theinput signal is sampled by using clock signals φ1, φ2 which constitute atransmission signal TX2 having the same phase information as thetransmission signal TX1.

The sampling converts the reception signal RX to a signal having afrequency of |fR·fT| and converts the transmission signal TX1 to a DCsignal.

The output signal of the sampling circuit 13 is passed through the firstLPF 14 a and second LPF 14 b thereby extracting separately a receptionsignal component with a frequency of |fR·fT|, which is a first LPF 14output, and a DC component signal, which is a second LFP output.

The DC component signal output from the second LPF 14 b adjusts theamount of delay of the delay circuit 17, that is, controls the samplingtiming of the sampling signal, so that the difference signal output fromthe op-amp 16 a approaches zero.

The reception signal component with a frequency of |fR·fT|, which is thefirst filter output signal, is input in the demodulation block 18located at the subsequent stage of the receiver 5 through the bufferamplifier 15.

FIG. 3 illustrates a configuration and operation of the sampling circuit13. The configuration of the sampling circuit 13 will be described firstwith reference to FIG. 3.

The sampling circuit 13 includes an amplifier, op-amp 13 a, for example.The sampling circuit 13 includes switches S1, S2, and S3 andcapacitances C1 and C2 in addition to the op-amp 13 a.

Switches S1 and S2 are turned on and off by the clock signals φ1 and φ2,respectively. An input signal (its input potential V1) and a referencesignal (its reference potential V2) are input into switches S1 and S2,respectively.

Switch S3 is turned on and off by the clock signal φ1, like switch S1.Switches S1 and S2 are controlled in such a manner that they are notturned on at the same time.

The input potential V1 and reference potential V2 input through switchesS1 and S2, respectively, are applied to an inverting input terminal ofthe op-amp 13 a through capacitance C1. A noninverting input terminal ofthe op-amp 13 a is grounded and capacitance C2 and switch S3 areconnected in parallel between the inverting input terminal and an outputterminal.

Operation of the sampling circuit 13 having the configuration describedabove will be described below.

When switches S1 and S3 are turned on by the clock signal φ1 and switchS2 is turned off by the clock signal φ2, capacitance C1 is charged witha charge corresponding to the input potential V1.

When subsequently switches S1 and S3 are turned off by the clock signalφ1, a charge corresponding to the input potential V1 at the instant ofthe switching-off is stored in capacitance C1.

Then, when switch S2 is turned on by the clock signal φ2, a chargecorresponding to the difference between the potential V1 at the instantof the switching-off of switch S1 by the clock signal φ1 and thereference potential V2 is transferred to capacitance C2. As a result, apotential of (V1·V2)*C1/C2 appears at the output terminal.

In the sampling circuit 13 in FIG. 2, the reference potential V2 in FIG.3 is set to the ground potential, zero, and the input potential V1 isequal to the signal voltage of the reception signal RX and transmissionsignal TX1 constituting an input signal. Accordingly, a signalproportional to the input potential V1 of the input signal is sampled bythe sampling circuit 13 and is output from the output terminal of thesampling circuit 13.

The clock signals φ1 and φ2 have opposite phases as described below.

In particular, the clock signals φ1 and φ2 are clock signals (binarysignals) having phases the timing of which is at a zero crossing of thetransmission signal TX1. The clock signals φ1 and φ2 have oppositephases (for further details, see FIG. 9 described later).

Operation according to the present embodiment will be described withreference to FIGS. 4A to 4F and 5A to 5F.

FIGS. 4A to 4F show operations of components of the reception signalextracting unit 11 before or during adjustment of the amount of delay bythe delay adjusting circuit 10. The horizontal axis of FIGS. 4A to 4Fand 5A to 5F represents time t.

A transmission signal TX1 and a reception signal RX are input in thesampling circuit 13 as shown in FIGS. 4A and 4B.

Because the transmitter 4 is located near the receiver 5, thetransmission signal TX1 (fT) is input in the sampling circuit 13 as aninterference wave or noise having an amplitude larger than that of thereception signal RX (fR).

The transmission signal TX1 (fT) and reception signal RX (fR) as inputsignals are sampled by using a transmission signal TX2 having phaseinformation of the transmission signal TX1, more specifically, the clocksignals φ1 and φ2 shown in FIGS. 4C and 4D.

Here, the transmission signal TX1 and the transmission signal TX2(specifically, clock signals φ1 and φ2) are signals generated from thesame signal and differ only in that the signals TX1 and TX2 are delayedor advanced as a whole with respect to each other in time t, that is,the signals TX1 and TX2 are phase-shifted in time with respect to eachother. Accordingly, when the transmission signal TX1 is sampled by usingthe clock signals φ1, φ2, almost the same level will be sampled andtherefore the sampling circuit 13 will output a signal that issubstantially a DC signal.

The output signal of the sampling circuit 13 includes a small amount ofreception signal RX information. However, only the DC component isextracted by the second LPF 14 b. FIG. 4E to the right of FIG. 4A showsthe output signal of the second LPF 14 b, namely the second LPF output.The second LPF output corresponds to a sampled value of the transmissionsignal TX1 shown to the left.

A first LPF output is shown in FIG. 4F below the second LPF output inFIG. 4E.

Because the second LPF output (DC component) is superimposed on thefirst LPF output, the first LPF output contains a noise component (theDC component of the second LPF output) larger than the reception signalRX.

The output signal of the second LPF 14 b is input in the op-amp 16 a anda control loop functions to control the amount of delay of the delaycircuit 17 so that the difference between the DC component of the secondLPF output and a reference potential of zero is reduced to zero.

With the control, the timing of sampling is set at the timing of a zerocrossing of the transmission signal TX1 as shown in FIGS. 5A to 5F andthe setting is maintained.

In the setting, the second LPF output becomes zero as shown in FIG. 5E.This means that the sampling at the timing of a zero crossing of thetransmission signal TX1 cancels the transmission signal TX1 so that thetransmission signal TX1 does not appear in the output signal of thesampling circuit 13.

Therefore, a reception signal component can be extracted as the firstLPF output in which the transmission signal TX1 is canceled as shown inFIG. 5F.

The reception signal component with a frequency of |fR·fT| extracted bythe first LPF 14 a can be represented by the product of the transmissionsignal TX1 and the reception signal RX. Because the frequency fT of thetransmission signal is known, demodulation of the reception signal witha frequency of fR is possible.

Additionally, the reception signal RX, which is originally a modulatedsignal, has been further (doubly) modulated with transmission signal TX.Therefore, the reception signal RX should be demodulated first on thebasis of the transmission signal TX and then further demodulated to theoriginal reception signal RX.

The present embodiment can be widely applied to cases where thefrequency fT of a transmission signal differs from the frequency fR of areception signal.

FIG. 6 shows an example of the result of a simulation of a receptionsignal component (simply expressed as reception signal in FIG. 6) and atransmission signal component (simply referred to as transmission signalin FIG. 6) obtained through the reception signal extracting unit 11 inthe state shown in FIGS. 5A to 5F. The vertical axis of FIG. 6represents the intensity of the signal components output from thereception signal extracting unit 11 and the horizontal axis representsthe input intensity of the reception signal.

When the timing of sampling is not set at a zero crossing of thetransmission signal TX1, the transmission signal component becomesgreater than the reception signal component as shown in the first LPFoutput in FIG. 4F.

In contrast, when the timing of sampling is set at a zero crossing ofthe transmission signal TX1 as shown in FIGS. 5A to 5F, a receptioncondition is achieved in which the reception signal is extracted withthe transmission signal component being cancelled to almost zero.

Accordingly, the transmission signal component is sufficiently smallerthan the reception signal component in the result of the simulationshown in FIG. 6. Here, the reception signal component varies inproportion to the input amplitude. Therefore, the reception signalcomponent can be appropriately demodulated.

Thus, according to the present embodiment, a target reception signal tobe received can be extracted in which a transmission signal TX1 that issignificant noise or interference wave interfering with the receptionsignal is cancelled or sufficiently reduced.

Furthermore, according to the present embodiment, a reception signalcomponent can be extracted with a transmission signal TX1 beingcancelled or sufficiently reduced by using a simple configuration.

A variation of the present embodiment will be described next.

FIG. 7 shows an exemplary configuration of a reception signal extractingunit 11B according to a variation of the first embodiment. In FIG. 2,the amount of delay is adjusted in an analog fashion and the samplingcircuit 13 samples an input signal at the timing of a zero crossing of atransmission signal TX1 in the input signal.

FIG. 7 shows an exemplary configuration in which the amount of delay isadjusted in a digital fashion. The reception signal extracting unit 11Bshown in FIG. 7 uses a digital delay adjusting circuit 10B whichslightly differs from the delay adjusting circuit 10 in FIG. 2.

An output signal of the second LPF 14 a is input in an analog-digitalconversion circuit (abbreviated as ADC) 21, where the signal isconverted to a digital signal. The digital signal is input in a digitalcontrol circuit 22, which controls the amount of delay of a delaycircuit 17 in accordance with the digital value of the ADC 21. The restof the configuration is the same as that in FIG. 2.

The output from the comparator 16 a in the configuration shown in FIG. 2is an analog quantity whereas the output from the ADC 21 in FIG. 7 is adigital quantity. The configuration has the effect that, as comparedwith the analog output, the digital output is easy to deal with byadjusting parameters, for example.

Other operations and effects of the variation are similar to those ofthe embodiment shown in FIG. 2.

In the variation, the amount of delay may be controlled (adjusted)constantly as in the first embodiment or may be adjusted periodically asshown in FIGS. 8A and 8B.

In the example in FIGS. 8A and 8B, control operation for adjusting theamount of delay of the delay circuit 17 is performed for an appropriateperiod of time T1 (see FIG. 8B) in synchronization with a verticalsynchronizing signal VD shown in FIG. 8A, for example. Then, the controloperation for adjusting the amount of delay may be halted for a timeperiod T2, for example, as shown in FIG. 8B. During the time period T2,the ADC 21 and the digital control circuit 22 may be placed in a powersaving mode such as a hold state. After the time period T2, the controloperation for adjusting the amount of delay may be resumed.

Typically, the positional relationship between a transmitter 4 and areceiver 5 rarely varies with time. Therefore, a reception conditionalmost the same as the reception condition that can be set to constantcontrol operation can be achieved by the periodic control operation foradjusting the amount of delay as shown in FIGS. 8A and 8B. Accordingly,the variation can provide the same effects as the first embodiment.

Periodic control operation for adjusting the amount of delay as shown inFIGS. 8A and 8B can save more power or can further reduce powerconsumption.

Second Embodiment

A second embodiment of the present invention will be described belowwith reference to FIG. 9. FIG. 9 shows a configuration of a receiver 5Cin a radio apparatus according to the second embodiment.

In the first embodiment, a control loop is configured that automaticallyadjusts the timing (phase amount) of clock signals φ1, φ2 for samplingin the sampling circuit 13 on the basis of an output signal of thesampling circuit 13 so that the timing is synchronized to the timing ofa zero crossing of a transmission signal TX1.

In the radio apparatus according to the present embodiment, on the otherhand, a delay adjusting unit 10C which constitutes a reception signalextracting unit 11C in the receiver 5C includes a setting unit 31configured to set the amount of delay and a variable delay element 32whose delay is variably set to a predetermined fixed value by thesetting unit 31.

In the radio apparatus according to the present embodiment, thetransmitter 4 and the receiver 5C are fixed in the radio apparatus.Accordingly, when a transmission signal cross-talks into an input signalinput in the sampling circuit 13 in the receiver 5C, it is unlikely thatthe cross-talk path changes with time.

Therefore, in the present embodiment, the amount of delay (referred toas the zero-crossing delay amount) corresponding to the timing of a zerocrossing of a transmission signal TX1 in the sampling circuit 13 orinformation on the amount of delay is determined beforehand in areceiver 5C to be shipped as a product, for example.

Then, the setting unit 31 is used to set the amount of delay to beproduced by the variable delay element 32 to that zero-crossing delayamount.

In this case, the setting unit 31 includes a memory 31 a, for example.Data representing the zero-crossing delay amount is written in thememory 31 a through a terminal Di beforehand so that the setting unit 31can use the data stored in the memory 31 a to set the amount of delay tobe produced by the variable delay element 32 to the zero-crossing delayamount.

The transmitter 4 includes a transmission signal generating unit 34configured to generate a transmission signal TX2 (specifically, clocksignals φo1 and φo2) from the transmission signal TX1.

The transmission signal generating unit 34 includes a zero-crosscomparator 34 a into which the transmission signal TX1 is input, abuffer 34 b configured to output an output signal from the zero-crosscomparator 34 a without inverting, and an inverting buffer 34 cconfigured to invert the signal and output the inverted signal.

The buffer 34 b outputs the clock signal φo2 and the buffer 34 c outputsthe clock signal φo1. The clock signals φo1, φo2 shown in FIG. 9 aredefined so that sampling is performed at a trailing edge of the clocksignal φo1 as shown in FIGS. 4A to 4F and 5A to 5F.

The present embodiment enables a reception signal to be extracted inwhich the influence of noise or an interference wave due to atransmission signal TX1 is cancelled or sufficiently reduced with asimpler configuration than that of the first embodiment.

The present embodiment can accommodate various placements of thetransmitter 4 and the receiver 5C simply by writing in a memory 31 adata on the zero-crossing delay amount determined beforehand for eachindividual model determined, that is, simply by changing data to bewritten in the memory 31 a from model to model.

Once written, the fixed value of the zero-crossing delay amount is usedto cancel or sufficiently reduce the influence of an interference wavedue to a transmission signal TX1 to extract a reception signal.

Thus, the present embodiment can accommodate various models.

If the path through which a transmission signal TX1 enters the samplingcircuit 13 is changed by maintenance of the receive 5C, the data writtenin the memory 31 a can be changed after the maintenance to appropriatelyaddress the influence of the transmission signal TX1.

According to a variation of the present embodiment, the delay adjustingcircuit may be configured with multiple delay elements (which may bedelay lines) having fixed delay amounts, and selection circuits, whichmay be multiplexers M1, M2, may be used to select any of the delayelements.

FIG. 10 shows a delay adjusting circuit 10D which is an example of suchconfiguration. In the delay adjusting circuit 10D, one delay circuit Dk(k=2 in FIG. 10) out of three delay circuits D1, D2, and D3 that producedifferent amounts of delay is selected by using multiplexers M1 and M2.A selection signal is applied to the multiplexers M1, M2 from a sourcesuch as a memory.

The delay circuits D1, D2, and D3 may be implemented by delay elements Dthat produce predetermined amounts of delay, for example.

The delay circuit Dk that produces the amount of delay closest to theamount of delay that provides the timing of sampling at a zero crossingof a transmission signal TX1 is selected. Both ends of each of the delaycircuits that are not selected are grounded to prevent noise from beinginduced. One delay adjusting circuit 10D in which clock signal φo1 isinput is shown in FIG. 10. In practice, another delay adjusting circuit10D having the same configuration is used for clock signal φo2.

As a variation of the delay adjusting circuit shown in FIG. 10, a delayadjusting circuit (correctly a delay setting circuit in this case)including only one delay circuit Dk for clock signal φo1 or φo2 may beused.

If the placement of the transmitter 4 and the receiver 5C is fixed, thepath through which a transmission signal TX1 enters the receiver 5C istypically determined, as stated above. Therefore, a fixed amount ofdelay can be set for the fixed path so that sampling is performed at thetiming of a zero crossing of the transmission signal TX1.

In this case, the influence of the transmission signal TX1 can becancelled or reduced very simply with a low cost.

Alternatively, a delay-variable inverter chain or the like used in a DLL(delay-locked loop) may be used to configure a delay adjusting circuit.

A gate circuit may be used to extract a reception signal component,instead of sampling. The timing at which the gate circuit opens may beadjusted in a manner similar to that for the timing of sampling in thesampling circuit 13, so that the gate circuit passes an input signal atthe timing of a zero crossing of a transmission signal TX1 with a shortgate width.

The present invention also includes embodiments configured by combiningany parts of the embodiments described above.

According to the embodiments described above, a reception signalcomponent can be extracted by canceling or reducing the influence of atransmission signal with a simple configuration when transmission andreception are performed concurrently.

Having described the embodiments of the invention referring to theaccompanying drawings, it should be understood that the presentinvention is not limited to those precise embodiments and variouschanges and modifications thereof could be made by one skilled in theart without departing from the spirit or scope of the invention asdefined in the appended claims.

1. A radio apparatus comprising: a receiver configured to receive as areception signal a wirelessly transmitted signal; a transmitter providedin the vicinity of the receiver and configured to generate atransmission signal to be wirelessly transmitted with a frequencydifferent from that of the reception signal; and a reception signalextracting unit provided in the receiver and configured to extract areception signal component from an input signal containing the receptionsignal and the transmission signal, at a timing of a zero crossing ofthe transmission signal in the input signal, by using phase informationincluding a phase of the transmission signal directly input from thetransmitter to the receiver, such that the transmission signal containedin the input signal remains only as a DC offset value in the receptionsignal component, the DC offset value corresponding to a phasedifference between the transmission signal in the input signal and thetransmission signal directly input from the transmitter; wherein thereception signal extracting unit extracts a reception signal componenthaving a frequency of |fR−fT|, where fR is a frequency of the receptionsignal and fT is a frequency of the transmission signal.
 2. The radioapparatus according to claim 1, wherein the reception signal componentextracting unit samples the input signal at a timing of a zero crossingof the transmission signal in the input signal to extract the receptionsignal.
 3. The radio apparatus according to claim 1, wherein thereception signal extracting unit comprises a sampling circuit configuredto sample the input signal by using a sampling signal based on a clocksignal having a phase of the transmission signal and a delay adjustingcircuit configured to adjust the phase of the clock signal by a timedelay to a timing of a zero crossing of the transmission signal in theinput signal.
 4. The radio apparatus according to claim 3, wherein thedelay adjusting circuit uses an output signal of the sampling circuit toautomatically adjust the phase of the clock signal to practically reducea DC component of the output signal to zero.
 5. The radio apparatusaccording to claim 3, wherein the delay adjusting circuit periodicallyoperates at predetermined intervals to adjust a delay amount.
 6. Theradio apparatus according to claim 4, wherein the reception signalextracting unit extracts a reception signal component having a frequencyof |fR−fT|, where fR is a frequency of the reception signal and fT is afrequency of the transmission signal.
 7. The radio apparatus accordingto claim 3, wherein the delay adjusting circuit automatically adjuststhe phase of the clock signal by using a preset delay amountcorresponding to a timing of a zero crossing of the transmission signalin the sampling circuit.
 8. A radio receiving method using a receiverconfigured to receive as a reception signal a wirelessly transmittedsignal, and a transmitter provided in the vicinity of the receiver andconfigured to generate a transmission signal to be wirelesslytransmitted with a frequency different from that of the receptionsignal, the radio receiving method comprising: detecting a timing of azero crossing of the transmission signal in an input signal, which isinput to the receiver and containing the reception signal and thetransmission signal, by using phase information including a phase of thetransmission signal directly input from the transmitter to the receiver;and extracting a reception signal component from the input signal at thedetected timing of the zero crossing such that the transmission signalcontained in the input signal remains only as a DC offset value in thereception signal component, the DC offset value corresponding to a phasedifference between the transmission signal in the input signal and thetransmission signal directly input from the transmitter; wherein areception signal component having a frequency of |fR−fT| is extracted,where fR is a frequency of the reception signal and fT is a frequency ofthe transmission signal.
 9. The radio receiving method according toclaim 8, wherein the reception signal component is extracted by samplingthe input signal at a timing of a zero crossing of the transmissionsignal in the input signal.
 10. The radio receiving method according toclaim 8, wherein a phase of a clock signal that is equal to a phase ofthe transmission signal in the input signal is adjusted by a time delayto a timing of a zero crossing of the transmission signal and the inputsignal is sampled by using the phase-adjusted clock signal.
 11. Theradio receiving method according to claim 10, wherein an output signalobtained by sampling the input signal by using a sampling signal basedon a clock signal having the phase of the transmission signal is used toautomatically adjust the phase of the clock signal to practically reducea DC component of the output signal to zero.
 12. The radio receivingmethod according to claim 10, wherein the phase of the clock signalhaving the phase of the transmission signal is adjusted periodically atpredetermined intervals.
 13. A radio apparatus comprising: a receiverconfigured to receive as a reception signal a wirelessly transmittedsignal; a transmitter provided in the vicinity of the receiver andconfigured to generate a transmission signal to be wirelesslytransmitted with a frequency different from that of the receptionsignal; a transmission signal generating unit provided in thetransmitter and configured to generate phase information of thetransmission signal; and a reception signal extracting unit provided inthe receiver and configured to extract a reception signal component froman input signal containing the reception signal and the transmissionsignal, at a timing of a zero crossing of the transmission signal in theinput signal, by using the phase information directly input from thetransmission signal generating unit, such that the transmission signalcontained in the input signal remains only as a DC offset value in thereception signal component, the DC offset value corresponding to a phasedifference between the transmission signal in the input signal and thetransmission signal directly input from the transmitter; wherein thereception signal extracting unit extracts a reception signal componenthaving a frequency of |fR−fT|, where fR is a frequency of the receptionsignal and fT is a frequency of the transmission signal.
 14. The radioapparatus according to claim 13, wherein the reception signal componentextracting unit samples the input signal at a timing of a zero crossingof the transmission signal in the input signal to extract the receptionsignal.
 15. The radio apparatus according to claim 14, wherein thereception signal extracting unit comprises a sampling circuit configuredto sample the input signal by using a sampling signal based on a clocksignal having a phase of the transmission signal and a delay adjustingcircuit configured to adjust the phase of the clock signal by a timedelay to a timing of a zero crossing of the transmission signal in theinput signal.
 16. The radio apparatus according to claim 15, wherein thedelay adjusting circuit automatically adjusts the phase of the clocksignal by using a preset delay amount corresponding to a timing of azero crossing of the transmission signal in the sampling circuit. 17.The radio apparatus according to claim 15, wherein the delay adjustingcircuit periodically operates at predetermined intervals to adjust adelay amount.